In ultrafine semiconductor integrated circuit devices today, a multilayer wiring structure having wiring patterns of a low resistance metal material is employed in order to interconnect numerous discrete semiconductor devices formed on a substrate. In particular, for a multilayer wiring structure having copper (Cu) wiring patterns, a damascene technique or a dual damascene technique is generally used in which wiring trenches or vias are formed in advance in a silicon oxide film, or in an interlayer dielectric film made of a so-called low-permittivity (low-K) material whose relative permittivity is lower than silicon oxide. According to the damascene or dual damascene technique, the wiring trenches or vias are filled with a Cu layer having low resistivity and high electromigration resistance, and excess Cu is removed by chemical mechanical polishing (CMP).
In the damascene or dual damascene technique, the surface of the wiring trenches or the vias formed in the interlayer dielectric film is generally covered by a barrier metal film typically made of a metal with a high melting point (e.g. Ta), or a nitride of such a metal (e.g. TaN). Subsequently, a thin Cu seed layer is formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD). Then, using electrolytic plating with the Cu seed layer serving as an electrode, the wiring trenches or vias are filled with a Cu layer.
In the Cu-layer electrolytic plating process, an electrolytic plating solution is commonly used, such as a cupric sulfate aqueous solution in which copper salt (e.g. copper sulfate) is dissolved in a polar solvent (e.g. water).
FIGS. 1A through 1E illustrate a process for forming a Cu wiring pattern according to a typical damascene technique.
According to FIG. 1A, depressions 12 serving as wiring trenches or vias are formed in a dielectric film 11. Next, as illustrated in FIG. 1B, a barrier metal film 13 is formed on the bottom and sidewalls of each depression 12, as well as on the top-field surface of the dielectric film 11, in a manner so as to follow the shapes of the depressions 12. The barrier metal film 13 is typically made of a high-melting-point metal, such as Ta or Ti, or a conductive nitride of such a metal, such as TaN or TiN, for example.
According to FIG. 1C, a Cu seed layer 14 is deposited on the barrier metal film 13 by PVD or CVD in a manner so as to follow the shapes of the depressions 12. As illustrated in FIG. 1D, by electrolytic plating with the Cu seed layer 14 serving as an electrode, the depressions 12 are filled with a Cu layer 15. The Cu layer 15 formed in this manner is also deposited on the top-field surface (flat parts) to form overgrowth regions commonly called “overplating”.
According to FIG. 1E, the overplating of the Cu layer 15 covering the surface of the interlayer dielectric film 11 and the barrier metal film 13 disposed under the overplating is removed by CMP so that the interlayer dielectric film 11 is exposed. Herewith, Cu wiring pattern portions 15A are obtained, which have few voids and high resistance against stress migration and electromigration.
However, in the recent manufacture of semiconductor devices having line-and-space patterns with a line width of 0.16 μm or less or vias with a diameter of 0.16 μm or less, the problem remains that, after the electrolytic plating process of FIG. 1D, unevenness in the in-plane distribution of the overplating increases at the periphery of a wafer W, which is an in-process substrate. If this unevenness is large, when subsequently the wafer W is polished by CMP, variation in the degree of so-called dishing increases. This then leads to variation in the wiring height and resistance within the formed Cu wiring layer, which in turn results in variation in the characteristics of the semiconductor devices.